1. Field of the Invention
This disclosure relates to a MOS transistor, and more particularly, to a recess gate transistor structure for use in a semiconductor device and a method thereof.
2. Description of the Related Art
Techniques for the manufacture and production of semiconductor devices are being developed worldwide, based on requirements of semiconductor users and semiconductor manufacturers. The semiconductor manufacturers are giving an impetus to research and development for enhanced high-speed, miniaturized, highly-integrated, large-capacity semiconductor devices with more stabilized and smooth operation. Thus, designing to integrate more semiconductor devices in a semiconductor chip of limited size reduces an interval between gates, causing a short channel effect, a leakage current, and other difficulties.
In order to solve these shortcomings it is well known in the art of a recess gate type transistor that a gate insulation layer is formed in both side walls and bottom face of a recess formed in a substrate, and then a conductive layer, such as polysilicon, fills the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar substrate. A recess gate transistor forming method according to the related art is described as follows, referring to FIGS. 1 to 4.
FIGS. 1 to 4 are sectional views sequentially illustrating a recess gate transistor forming method according to a related art.
Referring first to FIG. 1, a device isolation film 102, which defines an active region and a non-active region, is formed on a predetermined region of a p-type semiconductor substrate 100. Then a p-type impurity is implanted in the substrate, to thus form a well-region 104. Subsequently, a p-type impurity is ion-implanted into the active region defined by the device isolation film 102, to form a threshold voltage control region 106. Then, an n-type impurity is ion-implanted into the active region, to form an impurity induction layer 108.
Referring to FIG. 2, an oxide layer 110 and a masking layer 112 are formed, then a recess is formed on a portion of the active region through a photolithography process.
With reference to FIG. 3, a gate oxide layer 113 is formed within the recess, and then a polysilicon layer 114 is formed to fill the recess on which the gate oxide layer was formed. Next, a conductive layer 116 and a capping layer 118 are sequentially formed on the polysilicon layer 114.
With reference to FIG. 4, a gate stack is formed through a photolithography process, and an n-type impurity is ion-implanted with relatively low energy into the impurity induction layer 108 by using the gate stack as an ion implantation mask, to thus form an n-type source/drain region of low density. Then, a gate spacer 120 is formed in sidewalls of the gate stack, and impurity is ion-implanted with relatively high energy into the n-type source/drain region of low density by using the gate spacer as an ion implantation mask. That is, an n+ type source/drain region of high density having an impurity density higher than the low density is formed on a portion of the n-type source/drain region that was previously low density. Consequently, the recess gate transistor is obtained according to the related art. According to the related art, a leakage is generated by a concentration of an electric field because only a thin oxide layer is interposed between the active region and the gate. This, in effect, extends the contact region between the active region and the gate. This causes an increased load capacity and gate induced drain leakage (GIDL).
Furthermore, a length of the recess is formed smaller than a length of the gate in order to ensure a misalign margin, and this requires a high-level of precision in the photolithography process and causes a drop in a production yield of the semiconductor device.
Embodiments of the invention address these and other disadvantages of the related art.